Douglas W. Brown
email doug[at]DougAndJean[dot]com
home page http://www.DougAndJean.com

Objective

• Computation acceleration engineering, which includes designing hardware, designing tools for designing hardware, programming parallel hardware (FPGA, GPGPU, multicore microprocessors, compute farms, and clouds), developing libraries or tools for parallel hardware, or algorithm development and optimization.

Qualifications

• Proven track record solving world-class technical challenges.
• Reliable at scheduling tasks and meeting the schedules.
• Worked well with teams on large projects.
• Successfully worked on independent projects with little supervision.
• Fluent in verilog, and familiar with vhdl.
• Fluent in c, c++, perl(/tk), tcl(/tk), and familiar with python, haskell, ocaml, and many other imperative, functional, constraint-based, and term-rewriting system languages.
• Familiar with various commercial hardware design tools, including Design Compiler and Pearl.

Work History

• 2010 - 2013: Range Networks
  • Worked on various parts of the software for a mobile phone base station, all layers, from forward error correction encoding and decoding up to subscriber registry. These involved c++, perl, erlang, sql, curl, asn.1, and reams of GSM specifications.
• 2009 - 2010: Contract with stealth startup
  • Web server work involving java, c++, sql, axis2, soap, xml, curl, etc.
• 2007 - 2009: OptNgn Software
  • Developed FPGA compiler. This inputs scilab (similar to matlab, the favorite language for DSP designers), haskell, or behavioral verilog and outputs lower-level verilog optimized for FPGA synthesis. Initial use has been for pipelined FFT design.
• 2005 - 2007: Micro Magic
  • Developed technology mapper for high-speed ASIC datapaths. This inputs a generic technology netlist and outputs a standard-cell netlist optimized for a preselected tradeoff of speed and area.
  • Developed layout design-rule extractor. This inputs foundry reports, and outputs design rules for the MAX layout editor.
  • Developed schematic generator that inputs verilog and outputs schematics for the SUE schematic editor.
• 2003 - 2005: NVIDIA
  • Developed datapath generator that inputs verilog and outputs standard cells for high-speed datapaths. The standard cells are automatically placed, sized, buffered, and pre-routed. The tool also displays the layout, and annotates the display with congestion analysis.
• 2002 - 2003: Real Intent
  • Helped develop clock domain boundary crossing analysis tool.
  • Helped develop graphic user interface for formal verification analysis tools.
• 1998 - 2002: Micro Magic and Juniper Networks (which bought Micro Magic)
  • Helped design, layout, and verify high-speed datapaths.
  • Enhanced schematic editor.
  • Developed formal equivalence checking tool.
• 1997 - 1998: Portland Software
  • Helped design encrypted server-server and server-client communication software.
• 1996 - 1997: Summit Design
  • Developed automatic board test program compression.
• 1995 - 1996: Translogic Technology
  • Developed formal equivalence checking tool.
• 1994 - 1995: Lattice Semiconductor
  • Developed mixed-signal simulation tool.
• 1988 - 1994: Test Systems Strategies
  • Helped develop board test software.
  • Helped develop waveform editor.
  • Developed and ran software for release management.
• 1984 - 1988: Tektronix
  • Managed module generator project.
  • Supervised summer intern for AI project.
• 1981 - 1984: Metheus
  • Developed gui for analog and digital simulation.
• 1977 - 1981: Tektronix
  • Developed microprocessor design aid software.
  • Supported analog and digital simulation users.
• 1970 - 1977: University of Illinois
  • Helped develop PLATO computer-based education system.
  • Developed gui for interface to SPICE analog circuit simulator.

Publications

• C++, The Core Language , co-authored with Gregory Satir, O'Reilly & Associates, 1995.
• Lex and Yacc , co-authored with Tony Mason, O'Reilly & Associates, 1990.
• A State-Machine Synthesizer in the 18th Design Automation Conference Proceedings, June, 1981.

Education

• University of Illinois at Urbana-Champaign
• M.S. in Electrical Engineering, June 1976
• B.S. in Electrical Engineering, June 1974